Howard A. Landman

Goals

Currently not available. If I was, I would be seeking a leadership role driving either an integrated circuit design or the CAD/EDA tools and methodologies supporting one. Silicon Valley or Northern Colorado regions preferred.

Have done contract work in various parts of the world. Speak some Japanese and a little German.

Education

• BA Mathematics (Honors) w/ Chemistry minor, U.C. Berkeley
  placed in top 100 in U.S. in W. L. Putnam math competition
  Fanny and John Hertz Foundation Scholar; California Alumni Scholar
• Graduate study in Chemistry, Princeton U.
• MS Computer Science, U. C. Berkeley
  top score on theory prelim exam; co-designer of RISC-I microprocessor chip

1/05 (new job): Manager, Physical Design
Ageia Technologies, St. Louis, MO & Mountain View, CA

(description soon)

3/02 to 1/05: Independent EDA consultant

Client List:

• Applied Minds, Glendale CA
• Calix Networks, Petaluma CA
• Gerson Lehrman Group, New York NY
• Jack D. Grimes Consulting, San Jose CA
• Magma Design Automation, Santa Clara CA
• Synaptic Labs, Sydney & Brisbane Australia, Geneva Switzerland

3/99 to 2/02: Senior Design Engineer
Vitesse Semiconductor, ANP division (formerly SiTera Inc.), Longmont, CO

Staff position responsible for formal verification, technology evaluation, electromigration analysis, clock distribution, DRC/ERC runset development, and some RTL coding for the IQ2000 & IQ2200 network processors. Worked on 14 total tapeouts. Tools used include Perl, Tcl, Apollo/Milkyway, Hercules, Design Verifyer (Chrysalis), Design Compiler, Tetramax, VCS, Calibre, Verplex LEC.

11/96 to 1/99: Manager, Synthesis & Physical Design, Processor Development
Toshiba America Electronic Components, San Jose, CA

Led the logic synthesis and physical design of the processor for the Sony Playstation 2 "Emotion Engine" (first commercial 128-bit microprocessor). 7 people in my team. Developed and managed back-end schedule with only 14% slip. Much travel to Japan and coordination with Japanese managers & engineers. Wrote Logic Design Rules spec and co-wrote RTL Design Guidelines. Spearheaded use of Ambit (synthesis) and Chrysalis (formal verification) tools. First silicon was 100% functional; second silicon (speedup) shipped in development systems; third silicon (shrink & cost reduction) has shipped over 23 million units.

11/92 to 11/96: Senior CAD Engineer
HaL Computer Systems, Campbell, CA (later acquired by Fujitsu)

Corporate logic synthesis guru. Also developed Verilog library & validation procedure; methodologies and tools for post-layout backannotation, electromigration analysis, antenna-rule checking, netlist partitioning, & FSM coverage analysis. Responsible for QA of cell libraries. Heavy use of Perl.

5/91 to 11/92: Senior CAD Engineer
Crosspoint Solutions, Santa Clara, CA

Responsible for logic-synthesis-related products and libraries. Developed AI system in Perl and Prolog to generate optimal cell layouts from transistor netlists, which successfully replaced a human designer.

4/88 to 5/91: Senior CAD Engineer
Sun Microsystems, Mountain View, CA

Lead EDA engineer for MicroSparc (Tsunami) microprocessor: planned and helped implement entire tools flow. Patented method for handling multi-cycle paths consistently in timing analysis, simulation, and synthesis. Evaluated and benchmarked commercial logic synthesis tools. Was Sun's corporate "Synopsys guru".

1/86 to 4/88: Senior CAD Software Engineer
Intel Corp., ASIC Systems, Chandler, AZ

Evaluated silicon compilers in relation to Intel's processes, methods, and ASIC strategy. Led joint project with SCS. Developed netlist translators using lex, yacc, and C. Introduced UNIX into ASIC group, administered VAX/Ultrix system. Headed Software Quality Task Force.

9/84 to 11/85: Software Engineer
Silicon Compilers Inc., San Jose, CA

Wrote CMOS PLA, PAL, and ROM compilers and PLA optimizer for SCI's Genesil silicon compiler. Incorporated Espresso into Genesil. Maintained NMOS PLA, PAL, and ROM compilers. All code in C and extensions of C.

6/82 to 8/84: VLSI/CAD Designer
Metheus Corporation, Hillsboro, OR

Principal SW engineer for 10 programs in Metheus' CAE workstation. All work in C, UNIX. Negotiated with foundries leading to technology exchange agreements. Some technical marketing work with much travel.

"VEST Hardware-Dedicated Stream Ciphers", submitted to the Ecrypt Stream Cipher Project, June 2005
http://www.ecrypt.eu.org/stream/ciphers/vest/vest.pdf

"Stability Analysis of a Complete RTL-to-GDS2 Design Flow", Magma Fusion Users Group, Sept. 2003

"How Predictable Is Your Design Flow?", web seminar April 30 2003 (http://webevents.broadcast.com/cmp/wcs/detail.asp?event_id=5877)

"A High Bandwidth Superscalar Microprocessor for Multimedia Applications", ISSCC 1999

"Visualizing the Behavior of Logic Synthesis Algorithms", 1998 Synopsys User's Group.

U.S. Patent 5,191,541: Method and Apparatus to Improve Static Path Analysis of Digital Circuits, March 2, 1993

"Low-level Logic Synthesis", IDEA '91 Conference

"Design Environments at Sun: Logic Synthesis", Sun User's Group 89

"Logic Synthesis at Sun", CompCon Spring 89

"OPUSI: An Optical Digital Position Sensor", ICCAD 83 Digest of Technical Papers, September 1983

"Integrating Foundry Processes into the Engineering Workstation", Electro/83 Professional Program, April 1983

Automatic Layout of Optimized PLA Structures, Masters Thesis, U.C. Berkeley, 1982.

"PLA Tools" in Berkeley VLSI Tools, Bob Mayo (ed.), Computer Science Division, U.C. Berkeley 1982

"A RISCy Approach to VLSI", VLSI Design, 4th quarter 1981.

"VLSI Implementations of a Reduced Instruction Set Computer", CMU Conference on VLSI Systems and Computations, 1981

I've also published papers in pure math (game theory) and nanotechnology.

Industry Activities:

Program Committee, IEEE Symposium on Computational Intelligence and Games 2005

Board of Technical Advisors, PicoCraft Design Systems, 2004-

Board of Editorial Advisors, Integrated System Design magazine, 1997-99

Technical Program Committee, Synopsys Users Group, 1994-96

Senior Associate, Foresight Institute

Reviewer for Theoretical Computer Science and Journal of Combinatorial Theory A

Coach and judge for Odyssey Of The Mind; judge for Science Olympiad

©2005 Howard A. Landman, all rights reserved